One thing users get confused about is SLC caching. This is a relatively new technology as earlier consumer drives did not have SLC caching and were based on full SLC or MLC. Later MLC drives and then TLC drives, however, started using the technique to compensate for slower base flash. It’s confusing for two reasons: one, it’s not actual SLC, and two, reported speeds for SSDs are misleading as manufacturers will use SLC write performance instead of native when marketing their drives.
If it’s not native SLC, then what is it? It’s actually the base flash - whether 3-bit TLC or 4-bit QLC - switched to a single-bit mode. This single-bit mode, also known as pseudo-SLC, is faster because it only has to worry about two voltage states with the same amount of charge. Thresholds are therefore larger, making writes and reads faster due to lower latency. Programming in this manner is less harmful to the cells, as well, but this does not necessarily mean that pSLC will improve endurance.
Bits/cell and states
SLC caching comes at a cost - if you’re running 3-bit TLC cells in a single-bit pSLC mode, you only have 1/3rd the effective capacity. Eventually the data in SLC has to be rewritten to TLC so the blocks can be converted back over to get the full capacity of the drive. This is dynamic SLC, which can actually wear the flash further since data may have to be written twice. Some drives have a bit of dedicated or static pSLC which works a bit differently but serves the same purpose. Dynamic pSLC, on the other hand, is transitory and will work will all of the base flash.
Capacity from SLC caching
Our drives all have ample pSLC caches because that’s a good match for consumer and prosumer usage. Enterprise drives, which favor sustained performance and opt for endurance, tend not to use SLC caching. pSLC is useful for absorbing sudden, bursty workloads, and is faster for shorter write periods. We make sure to tune our NVMe drives around offering the best experience for our customers - which means making sure the drive has adequate cache over a variety of conditions, while be wary of edge cases.
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